xv6, line by line
about the creator
Portrait of Jyotiprakash Mishra

The creator of xv6, line by line

Jyotiprakash Mishra

  • Assistant Professor of Computer Science, KIIT
  • Co-founder and CEO, ENineHQ Technologies
  • PhD candidate (thesis submitted), BITS Pilani

Computer scientist, teacher and engineer — sixteen years across enterprise software, healthcare technology, university teaching and hardware-security research on RISC-V.

mail@jyotiprakash.orgblog.jyotiprakash.orgeninehq.comLinkedIn
16years of experience8 in industry · 8 teaching
2booksDe Gruyter Brill, 2026
6published patentsRISC-V hardware security
16research publicationsincl. Scopus Q1/Q2 journals
437K+YouTube views78 free OS & networks lectures
4teaching simulatorsone live, three in closed testing

A note on the project

Why this site exists

This site is the companion to RISC-V Architecture and XV6: Instruction Set Architecture, Systems Programming, and Kernel Development (De Gruyter Brill, 2026). It grew from years of teaching operating systems — first as the graduate teaching assistant for Introduction to Operating Systems at the University of Wisconsin–Madison, then in lecture halls at KIIT and in seventy-eight free lectures on YouTube — and from a conviction that a student should be able to see everything: every line of a real kernel explained, every claim checked against the code, every experiment actually run. The annotations, tours, concept pages, the 500 self-graded questions and the extension labs were designed and directed by Jyotiprakash Mishra, and every fact in them was verified against xv6 running on QEMU.

Profile

Over fifteen years spanning enterprise software engineering, healthcare technology leadership, university teaching and hardware-security research. Doctoral research at BITS Pilani on the security of the hardware–software interface — microarchitectural side channels, memory encryption, and hardware-assisted malware detection on RISC-V — with the thesis submitted and the degree expected in December 2026. Educated at BITS Pilani and the University of Wisconsin–Madison, graduating with distinction from both; the MS at UW–Madison was fully funded through a guaranteed teaching assistantship. Formerly a Team Lead at Epic (USA) and Senior Member of Technical Staff at Oracle.

De Gruyter Brill, 2026

Books

Approved

RISC-V Architecture and XV6: Instruction Set Architecture, Systems Programming, and Kernel Development

Jyotiprakash Mishra and Sanjay K. Sahay
De Gruyter Brill, Berlin, 2026 · ISBN 978-3-11-227456-9

The book this site accompanies.

In press

Cryptographic Foundations: Symmetric and Public-Key Cryptography, Hashes, Digital Signatures, and Protocols

Jyotiprakash Mishra and Sanjay K. Sahay
De Gruyter Brill, Berlin, 2026 · ISBN 978-3-11-226702-8

Free, in the browser

Teaching tools

µSystem 8086: The PC/XT board, wired chip by chip, that boots FreeDOS
The PC/XT board, wired chip by chip, that boots FreeDOS

Available now

µSystem 8086

A cycle-accurate 8086/8088 system simulator — wire period-correct chips pin by pin, step by cycle, probe any wire. The CPU core is 100.00% exact on all 3,007,000 SingleStepTests cases and the PC/XT preset boots FreeDOS 1.3.

8086.jyotiprakash.org →
PipeLens: Data hazards on the five-stage pipeline, cycle by cycle
Data hazards on the five-stage pipeline, cycle by cycle

In closed testing

PipeLens

Pipelines, caches and coherence in one explained, verified, offline simulator. RISC-V programs run on six textbook processor models — from the five-stage pipeline through the CDC 6600 scoreboard and Tomasulo's algorithm to an R10K-style out-of-order core — behind a configurable hierarchy of caches, coherence, networks, DRAM and several cores. Every cycle of every component is explained, and every run is checked in lock step against a reference ISS and a golden memory.

NetSim: A first ping: ARP and ICMP in the sniffer, decoded to the byte
A first ping: ARP and ICMP in the sniffer, decoded to the byte

In closed testing

NetSim

A browser network simulator — build IPv4 networks, send and sniff byte-accurate packets, step TCP congestion control, routing, VLANs, NAT and 802.11.

Compy: A use-after-free caught and explained, with the process memory map
A use-after-free caught and explained, with the process memory map

In closed testing

Compy

Every phase of a from-scratch C89 compiler opened up, with programs running over an inspectable memory model that catches and explains classic C bugs.

Education

2021 – 2026 (expected)

PhD in Computer Science

BITS Pilani, India

  • Thesis: An Investigation of Side-Channel Security in Open-Source RISC-V Processors — submitted; degree expected December 2026.
  • Hardware security of RISC-V processors — side-channel attacks and defenses, memory encryption, formally verified countermeasures, on-chip ML inference for real-time malware detection.
  • Advisor: Prof. Sanjay K. Sahay.

2014 – 2016

MS in Computer Science

University of Wisconsin–Madison, USA

  • GPA 3.9 / 4.0, systems concentration, graduated with distinction.
  • Fully funded; Graduate Teaching Assistant for Introduction to Operating Systems throughout.

2006 – 2010

BE (Hons.) in Computer Science

BITS Pilani, India

  • CGPA 9.53 / 10 with a perfect 10.0 in the first year; graduated with distinction.
  • Course topper in Advanced Computer Organization, Microprocessor Programming and Interfacing, Compiler Construction, Discrete Mathematics, Computational Physics and Embedded Systems Design.

Experience

  1. 2022 – present

    Co-founder & CEO

    ENineHQ Technologies

    An engineering company across three verticals — custom silicon and RISC-V processor design (FPGA prototypes to production SoCs, with a focus on hardware security), clinical-grade healthcare software, and security research consultancy.

  2. 2020 – present

    Assistant Professor

    KIIT, Bhubaneswar

    Teach computer architecture, operating systems and programming; research hardware security, RISC-V, malware analysis and cryptography.

  3. 2015 – 2020

    Team Lead, previously Software Developer and Intern

    Epic Systems, Madison, USA

    Led the team building specialty healthcare software for Epic’s international customers; built the Java backend serving medical data to Epic’s Rover mobile application.

  4. 2014 – 2016

    Graduate Teaching Assistant, Introduction to Operating Systems

    University of Wisconsin–Madison

    Taught operating-system concepts, set and graded examinations and weekly assignments, held office hours.

  5. 2010 – 2014

    Senior Member of Technical Staff

    Oracle, Bangalore

    Built Oracle Web Services Manager modules securing SOAP services across WebLogic, JBoss and WebSphere, and the management APIs of Oracle Entitlements Server.

  6. 2008 – 2010

    Research and engineering internships

    Yahoo! Labs, Bangalore · Bhabha Atomic Research Centre, Mumbai

    Web information extraction at Yahoo! Labs; at BARC (one of 16 selected nationwide), an algorithm for structured 3D grids on spline surfaces, validated on a BARC supercomputer.

Six published patent applications

Patents

Inventors: Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra and Aman Pathak

  1. IN202631036811 A1Hardware data-flow integrity monitor with register-file provenance tagging for RISC-V IoT processors
  2. IN202631036812 A1Hardware-accelerated microarchitectural event classifier with programmable feature extraction pipeline and on-chip ensemble inference engine for real-time malware detection in RISC-V processors
  3. IN202631036813 A1Per-peripheral cryptographic session engine with hardware key rotation for RISC-V IoT system-on-chip
  4. IN202631036814 A1On-chip binary decision tree inference engine integrated with RISC-V trace encoder for real-time IoT security monitoring
  5. IN202631036815 A1RISC-V processor architecture with tiered-memory ISA extension, tier-aware translation lookaside buffer, and Thunderbolt-attached external DRAM expansion with RISC-V bridge controller for Linux-based heterogeneous memory systems
  6. IN202631036816 A1Programmable instruction fusion engine with SRAM-based rules table for RISC-V IoT processors

Sixteen papers

Publications

  1. ESCI · Scopus Q2
    PACE: A Page-Adaptive, Cache-Anchored Memory-Encryption Engine for RISC-V with Formally Verified nth-Order DPA ResistanceChips 5(3), Article 25, 2026
  2. ESCI · Scopus Q1
    ARCHER: A Cycle-Accurate RISC-V Emulator for Microarchitectural Side-Channel and Memory Encryption ResearchComputers 15(8), Article 479, 2026
  3. ESCI · Scopus Q2
    Novel Microarchitectural Side-Channel Attacks on Open-Source RISC-V CoresChips 5(3), Article 29, 2026
  4. Scopus
    The Walk Is the Channel: Page-Table-Walker Cache Partitioning for Deterministic Domain Isolation on Out-of-Order RISC-VIEEE ISED 2026 (accepted)
  5. Scopus
    Closing a Spectre-v1 Cache Leak on BOOM with a Per-Domain GuardIEEE ISED 2026 (accepted)
  6. Scopus
    No-Op or No Security? A Backward-Compatible, Discoverable, Fail-Closed Contract for Security Directives in the RISC-V HINT Encoding SpaceIEEE ISED 2026 (accepted)
  7. Scopus
    History Is the Channel: Why Index Coloring Cannot Isolate a History-Based Branch Predictor, and a Warm Per-Domain Fix on Open RISC-V RTLIEEE ISED 2026 (accepted)
  8. Scopus
    Catching the Set Builder: Hardware Detection of Eviction-Set Construction at the Shared LLC on RISC-VSpringer CCIS, COCOLE 2026 (accepted)
  9. Scopus
    The Replacement Policy Is a Side Channel: Closing the Reload+Refresh Leak at the Policy Level on RISC-VSpringer CCIS, COCOLE 2026 (accepted)
  10. Scopus
    Memory Security: From Cold Boot Attacks to Side-Channel Defenses11th ICTIS, Springer LNNS 2026 (accepted)
  11. Scopus
    Formal Verification of Software-Managed Cache Coherency for RISC-V Heterogeneous Embedded SystemsSmartCom, Springer LNNS vol. 1997, pp. 430–442, 2026
  12. Scopus
    RV-JOSH: A Hardened Operating System for RISC-V based on JavaSmartCom, Springer LNNS vol. 1991, pp. 390–401, 2026
  13. Scopus
    Cache and Speculative Side Channel Attacks: A Comprehensive ReviewICT4SD, Springer LNNS, pp. 219–233, 2025
  14. Scopus
    A Hardware Security Review of RISC-VICT4SD, Springer LNNS, pp. 409–422, 2025
  15. Preprint
    Modern Hardware Security: A Review of Attacks and CountermeasuresarXiv:2501.04394, 2025
  16. Core-C
    Duplicates in the Drebin Dataset and Reduction in the Accuracy of the Malware Detection Models26th IEEE APCC, pp. 161–165, 2021

Honors

Expertise

Hardware securityMicroarchitectural side channelsMemory encryptionRISC-V ISA & microarchitectureVerilog / RTL, FPGAOperating systems & kernels (xv6, Linux)Systems programming in CCycle-accurate emulationFormal verificationCryptographyJava, Spring Boot, microservicesTeam leadership

Credits and license

“xv6, line by line” is created by Jyotiprakash Mishra. © 2026 Jyotiprakash Mishra.

  • Text, tours, concept pages, glossary, questions, lab write-ups and figures: CC BY-NC-SA 4.0. Share and adapt them for non-commercial purposes, under the same license, crediting “xv6, line by line” by Jyotiprakash Mishra, https://xv6.jyotiprakash.org.
  • The site software (generator and browser code): GNU GPL v3.0 or later, with an additional term under section 7(b): derived works must keep the attribution “Based on ‘xv6, line by line’ by Jyotiprakash Mishra (https://xv6.jyotiprakash.org)”.
  • The extension-lab reference solutions (xv6-riscv-labs): the author’s changes are GPL v3.0 or later with the same attribution term; xv6 itself stays MIT.
  • This page (biography, photograph, screenshots) and the product names: all rights reserved.
  • xv6 is by Frans Kaashoek, Robert Morris and Russ Cox at MIT, under the MIT license; its source code shown on this site remains under that license.

The full map of what covers what is in the NOTICE. For commercial use, write to mail@jyotiprakash.org.